In many applications the requirement of increasing computation speed renders the use of traditional arithmetic logic circuits more difficult.
The most-widely used technique in designing arithmetic logics is that of implementing minimized Boolean equations obtained by applying Karnaugh maps to the truth tables of the operations to be carried out, by suitable combinations of known elementary logic gates, such as NAND, NOR, NOT, EX-OR. Each elementary logic gate is then converted into the equivalent transistor circuit in the desired technology, e.g. integrated MOS technology. Finally the geometric dimensioning of the individual transistors of the structure to be integrated is effected. For example, in the case of an adder a structure is obtained consisting of equal addition cells, whose number is equal to the operand size and wherein the carry propagates from the least weight cell to the highest weight cell, through the various logic levels of each cell. The result will be stable at the output only at the end of the carry signal path. Hence carry signal propagation time limits computation speed, mainly when the operands have considerable size, and the number of levels of the logic to be traversed is high.
This is mainly due to the fact that in known circuits, the carry signal at the output of a cell generally feeds a considerable number of transistor gates of the subsequent cell. Thus the switching time is high because of the parasitic capacity, equivalent to the number of gates, seen by the output of the carry signal at the input of each the subsequent cell. The parasitic capacity is proportional to the number of transistor gates at the input.